Semiconductor devices such as integrated circuits (“IC”) or chips are formed with a plurality of bonding pads on the surface, and provide an on-chip interface to electrically couple signals on the semiconductor devices to external pins off-chip. As the size of ICs decrease with advancing technology, the pad size and pitch do not decrease at the same rate. Consequently, a greater percentage of area on an IC is taken up by bonding pads and their related structures.
FIG. 1A is a plan bottom view of conventional IC 100 which includes bonding pads 125. FIG. 1B is a cross-sectional view of a portion of IC 100 and one bonding pad 125. IC 100 includes bonding pads 125, semiconductor substrate 130, and metal stack 140. Metal stack 140 includes metal interconnect layers M1, M2, M3, and M4 formed within dielectric layer 150. Contacts 160 couple one metal interconnect layer of metal stack 140 to another metal interconnect layer. Inter-layer dielectric (“ILD”) 170 isolates semiconductor substrate 130 from metal stack 140.
One drawback of the above-described bonding pad structure is that a large portion of semiconductor substrate 130 is removed to accommodate bonding pad 125. Therefore, there is a reduced amount of semiconductor substrate 130 for circuit formation. With the percentage of area of an IC taken up by bonding pads increasing, bonding pad structures capable of supporting circuits under the bonding pad are needed.